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27號(hào)補(bǔ)丁修復(fù)的BUG較多！
6 W& R. J4 x8 z4 v, n百度網(wǎng)盤下載鏈接http://pan.baidu.com/s/1mgwSsPy/ O5 r3 s" v8 w) [1 [
2 y( q d- F2 ~3 U1 {; v
DATE: 04-25-2014 HOTFIX VERSION: 027
b# q/ M# r9 p+ [1 ^9 f* W7 \===================================================================================================================================
# z& G6 i$ @# y9 @5 dCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 n2 w: K8 V% |, Z0 h===================================================================================================================================3 G' l" H$ Q! o W7 E& z% M$ K
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM, P0 C1 d6 R6 @% T! x
481674 allegro_EDITOR pads_IN No board file saved from pads_in
7 B6 B3 k5 s4 P* ^+ e982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
2 x) `. y! e; U( o" ~2 |1012783 FSP OTHER Need Undo Command in FSP
+ ~6 i* c1 E! `" q" i5 B+ j1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.. C l" Q' N7 p8 V& I k
1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved7 l6 A% Z' @% ?2 f6 r: Z( u
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
# ]& x; U6 i# r% H: m0 r, o1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups6 K9 H o1 e8 Z( H2 }
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash' g! s! Q# e! \# G! A
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
7 o1 a: p6 N. ^) d& S1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode. t- W; n- U! G, v1 A- q: Q/ u
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
) x' }: |# U9 x* b1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
* w: g$ B5 O1 U/ I) }4 G" G" N1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings4 ]5 U: ], B4 D" |
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.- ~7 M) k4 n; V* z4 d3 N! m
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
) I7 L. E1 a# ], h$ v1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.+ f7 j# F% e9 L4 N
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
4 f; V9 { X* k3 q* b1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
: k- P! [7 ~ f: w1 U! ]* R9 P2 j1208478 PSPICE PROBE Attached project gives overflow error with marching ON.4 N$ h/ N, k+ S. |
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
1 {6 S: y7 f; x* O* H) R& u1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
+ u/ C9 U" Z* ^3 X& }8 e* h1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape' ?; ? x& z9 ]1 M
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
% I" K! z1 `" L3 f) n- b1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?2 v) f5 V* L+ {
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
4 f8 [+ ?' M- A- l1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
+ Q6 I2 z' B2 x, {1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
4 L7 U- [& u$ n: O* p9 \/ E2 [1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
0 o! ^4 p9 S% D# ~7 ]1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added! }5 I5 s- K9 m1 t
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.9 w S) F0 e0 W! D
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
$ E/ r G. V# M5 \! r7 c1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
9 J- y& k7 x! x! S5 D1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
6 [4 f1 ^( v; r- {1221182 ADW TDA Team Design with SAMBA- v* G5 c) o0 c+ v
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair& q0 Z5 U5 i3 J: e! M# c R
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened; c5 t R7 G/ c u2 ?1 U. f
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?7 {+ S$ }- x: t" |9 R- f
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts& U/ Y& @6 j# \( r# R
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms6 O7 W3 d9 {1 H5 f! \0 D
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
8 J1 y# O$ t+ ?, |8 ^6 h' ^1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor# r, ~$ ?$ A* ^# u
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
: l: j- u- p" d, Q- Z1 `1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
- ]& Z& {8 i8 k7 a1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin5 q5 m- Z7 b2 v9 I. I; j7 I
1225494 CAPTURE DRC Different DRC results for Entire design and selection, f! `3 Z3 x, v. r# f
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
4 j* a% Q }8 `/ H' F1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
8 C. ?$ h- ^5 A+ j3 d6 d1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
8 e6 \! c. ~7 m: j1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal0 Z# ~. m. x* x {" R) G
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
7 N& n- k1 [6 b5 [1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
/ s+ H. n8 m( ]6 C1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8% M" P @1 h6 g! N
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration5 |5 _9 ]. m2 u7 O8 e7 q
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part3 L. N9 K8 e/ T( s: A1 U+ C) o
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
- A* a4 | X& X2 l* S1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins) c2 G: n! {9 R2 L( o, a
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection0 k; Z5 W2 ]' h( Q
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
7 ]6 Q* u4 \6 { l5 e, Y1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
) g/ c0 U! ^$ ^- |8 L1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).0 E( P5 L. y5 Y# q; r
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM' N _% w2 n/ e
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined* o' A+ h9 { U9 z- Y' E
1230432 CONCEPT_HDL CORE No Description information in BOM
: B# J5 \' y2 J, M3 i& G* ~1 m1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
' F M) g3 C- j7 O: \1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
& j' I, ^7 m0 O% x. A% `) t0 L4 P1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
y6 L, R9 Q& X, U& g2 G9 l1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
: N9 Z2 l9 _7 |" j0 h# }! n( X. |1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
5 A2 s9 c& H- H" l1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode D2 n$ _% o( x# d2 y
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
5 B# ~% b1 k6 a) S- j/ a1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode8 L" Z8 o0 ~7 V8 i7 G: R8 L- L& T
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
1 I* Z9 E. b0 l! o: q1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy, _! P9 Q- ~& v3 L* L
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved: h( j l; g. d9 o# Q1 E
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect" d" R+ i6 k d: b% l0 e
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
" n8 L. L# I' H* P: c: [, b4 v1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic4 C/ w1 |( o [2 u
1236161 CONCEPT_HDL CORE Import Design shows the current project pages
7 e& \7 m* |, ]; u5 G; \6 v1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
' u4 ~" i0 y7 X# ]1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion6 e; | J8 r$ M( }3 V+ t+ F
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
: X; F/ P; f( m' E$ G: g8 A) ~1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
0 I5 V, @$ X6 d) f# x% X! m; C0 Y. R; W1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
, O. m7 I: O4 j9 B1236781 F2B PACKAGERXL Export Physical produces empty files; T8 q. ^* G6 U, ?$ x
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
7 t# ~& Q# @ d3 d1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
& p4 g( ^- w, q/ G t+ P5 n1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition, k' m, L2 v' y) P" P
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
/ q+ ?2 E9 M' e/ l1238852 CAPTURE GENERAL signal list not updated for buses+ s+ X0 K6 ~$ c' f
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes( _, {- h+ G4 p, A. _' C
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.$ D. A6 F3 a+ l" M* e
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
/ j8 j3 m, c* A# t1239763 PSPICE PROBE Cannot modify text label if right y axis is active
" [! B) M: }- x% g3 {) ^" s# M1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images; F! Y% \* ]2 }# Q) c
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
' Y5 K! t( g. \" I/ v# Q, _1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing7 j6 |& r+ H. H5 h$ W( E- `
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file- M* k R/ A" J. B7 J$ `: P8 J
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable; n6 Z4 w8 E7 {
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
, G" F; g, \ J% L* a. X1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms: s3 k% _/ d2 m5 h
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working/ @5 S% Z9 H" X
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
9 ^* j! }5 H; R, }1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard8 P! ^ x0 V, y0 y
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning, n3 z. | _ r& |1 N" V- U
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side2 z9 {8 L* |" n! a) E9 s2 v# _
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer) Q( H+ z* W( L( \8 b' i$ F
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
# x6 p1 l3 h3 j, d1243609 CONCEPT_HDL CORE autoprop for occurrence properties+ {, T$ k0 B3 ]" Z7 x3 g
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
) _! j4 v) Z9 t- J( J8 x1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
- r5 d! z& H6 f/ `3 K1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
& U- @2 v+ c+ C' L: v' O+ R1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder& [8 q) f9 n: O4 M1 g* A* r/ Q U
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
5 l2 u/ e* L/ |6 \& ]1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
% s9 L# f2 L& `8 z, \+ ~4 X1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?% s; S3 `4 k, w$ y
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
- v% O4 Z. n9 C+ Y8 }& F4 R1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters) V- q, X. N5 U" M
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown. `, Z" j8 D) _3 y* X
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
4 L7 \+ E6 h& m+ Y1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL% o% N" _5 [' U& k6 n. R
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
0 V& K. T3 G, K. z& N1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
% r4 i2 R! K& p1 K3 U- A% ^& S1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered# n8 l9 X- J4 T5 H8 p# C, a
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
7 V$ C! p: n0 I2 f+ }1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
% r$ S- E, X: [5 M) X) b. a3 Z5 S1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.3 ^% s; r* z) e1 l+ b! J# i
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
+ a5 i1 A/ a8 ^; W2 G& p" u: e- \1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly9 s0 b' ]- \0 t! L3 K' \. Y8 W
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.3 u j6 Z- D% `4 E- Q7 `) p }
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies! M* f* N6 y# ?4 o0 `) i
1253424 SCM SCHGEN Export Schematics Crashes System Architect
+ I( O+ R& J; u% [0 Q3 T& d% Q1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
1 i3 y' Q& x& E0 d3 J% s- u1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing$ ^3 y9 M" _! x u4 r' I! [- F2 L
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router$ O) g# h" ] Q4 o0 Q
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
) p$ |, c! w# ?+ h1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
7 a- Q% q' l6 U4 V- V* }1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation( n# e3 H% b; J7 ]& P% B
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects* u+ d* k0 b8 p0 @, a. B. G3 T: T) }5 K
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode2 B) o$ w, }4 m% e# A2 ^
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided7 N& x8 g; I$ V. k. c
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
4 o; r+ v- e* I% F/ `2 I2 r1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
+ k4 }' @2 }9 R6 v1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
7 j5 U% X5 I4 M& a3 W6 G# ?5 _1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library1 S; W3 Y' M; P, V, Q- _
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
( j% d( ~" n/ D# M1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash$ ^) B) G2 B3 t2 x$ z& \6 d
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time: V& b1 f( r2 ]) d; x! b/ R5 c" d
1258029 APD WIREBOND The bondwire lost after import the wire information1 C2 T0 p/ z" M& m3 F$ e
1258979 APD NC NC Drill: There is difference of number of drills. J& x& D1 i8 d; x- `0 u' K8 g
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
( W5 t+ \0 l4 w5 S5 G1 D, ?# W1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
7 Q& H9 G) u+ Z) }1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
( F; t; ]1 P1 d: {8 a! Y' _1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines" p1 |+ k) ` Y, v
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
4 w8 q2 j: ^2 |5 A) {/ R1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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