|
|
27號補(bǔ)丁修復(fù)的BUG較多！
9 c* n1 ?4 O/ x2 k4 G百度網(wǎng)盤下載鏈接http://pan.baidu.com/s/1mgwSsPy
- Q) a; @+ c! w% ~1 W$ f2 }8 ?8 [" J) w! x3 P
DATE: 04-25-2014 HOTFIX VERSION: 0271 n& p$ }/ H$ d; ~! G1 N3 s
===================================================================================================================================
( F, j4 k! i* H- t$ M8 X' TCCRID PRODUCT PRODUCTLEVEL2 TITLE) Y: o9 w7 E. B) X/ f6 X# n
===================================================================================================================================3 `) `% S8 J" e
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM' t% _9 ~0 P4 Q2 D F7 u! h4 A
481674 allegro_EDITOR pads_IN No board file saved from pads_in
1 t5 A' j" t( ~. B }% l982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
$ X4 {. H2 ?1 s1 R) B2 B1012783 FSP OTHER Need Undo Command in FSP
4 u7 V1 Y- b. ^ S& l0 v1 K1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
@. N4 [; Q0 O, n) a1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved- \ \! J' ?2 L& s' j$ Z
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.. c) d2 o( m7 s( @
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
3 @! n- E8 R3 i5 m o4 @" t r1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash; b+ a; E A. E2 w; F8 `1 M5 g& C
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command- ?7 ^8 Q! I! ^
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
( w: [% V# o# J1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
7 w/ d4 [! Q, J! T! v1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
1 _2 _: \+ h4 u. }8 [7 `7 U1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
' f+ g' S+ I3 F9 j/ I1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.- M+ M+ E+ D5 S( Q
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
* G' d5 M/ z5 X/ D3 i1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
' X: u0 |6 C/ H2 S1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates. b6 N/ Y% J) R& o* [* A
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime0 i8 _5 D$ C* Z+ C
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.7 v( y& W) w- _! F, B! @
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol$ Y0 Q% u; E. |& E7 `( _& O
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
% |* u( k% ~& U# }0 ]1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape0 P& ~/ d7 y I( P( i6 }# ]* x
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers- a! ]# L9 ~0 o5 y
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
* q. f3 b2 m3 \0 g1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.2 \, ]. X3 e) C& Q7 j: h
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
$ i6 d3 P( o& M! p: O1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
1 I2 J) ?$ ^5 M& i8 c6 X1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
+ _8 ?2 b! z; h. _9 I$ i1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added$ @; }" w: s) Q
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
8 e/ a n, W% F+ G$ M; Z7 f8 P1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
, u; Y: o- ^ ]# ^, o+ x: E1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux
: l1 T, Y1 }/ |4 g- {( j1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
( ?3 P) `4 q, L$ h2 b% t4 Q1221182 ADW TDA Team Design with SAMBA8 Z1 }8 j: f1 `5 m7 V( C
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
6 m/ q- F! U- f4 \$ F. t1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened% E! x( U" J& k, s0 M. G
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
. ]- d4 q# v6 H/ I' H' O6 v2 d) B1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
4 y, V1 L5 q* K: y9 k. O/ H" t1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms/ [ R7 D8 q5 E
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
: ]' N3 Q: [* O1 D# ~/ s5 }, r6 X0 J! x1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
0 u1 Y0 S, H: R$ ~1 p% x/ E2 _1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.1 W" b2 a l% _# o
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path- `- I7 G# `3 ~: g
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
5 \/ D; Y" n: z. a$ P Q9 F1225494 CAPTURE DRC Different DRC results for Entire design and selection
8 f- \4 j! @6 |. Z4 y# i* s1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
. i- ]* B t- [! I1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet; J0 B. Z3 K* [ p$ U7 L2 M V* |, W
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
3 Y4 o8 k! F- i8 r* ]1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
) f8 f* z3 x. H9 M1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file/ q2 B0 G! |- f8 {
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors( E6 X! ~8 q9 o1 s5 ~% g. Y
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
% ]2 L, P7 ~! D' `. h' k8 d3 ?1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration6 y* |+ Q# E& V
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part5 o9 W0 I9 U0 R' f$ N& [7 ~& s
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case. h& o9 v, Y6 z0 C; e, F+ p
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
/ p( Q8 `/ O8 J3 g1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection& C+ X7 r& e& \) @9 H- o
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.1 p4 a' ], _# \
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
' d% g- ^4 S* B" Y1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).: I, u3 }- {) `; o
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
* b/ _) p. J" Y0 j& L8 i1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined: J5 A. l) f) W3 o# R, W, H& I
1230432 CONCEPT_HDL CORE No Description information in BOM! m: M0 j; X ` G0 f: Y8 j
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes: z. I* x9 t) H. p
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
* I" U$ v6 R' E% f2 G1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
* H5 j: _/ A" w1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets7 Z7 ~1 f- Q! {4 b8 k$ H; }2 B
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.8 o. o5 u9 T3 i. p) t
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode
' N6 a. D# k$ U6 h* w0 c1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical& F) Y0 ^- O1 i% z1 C. R
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode& K( w6 N) [: V' g1 X
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files: L2 P" e: q% s8 C3 \* T
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
6 q. X! ^) t" E' t0 `* P# h1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
" I6 Y1 ]- `) P4 d2 I2 }9 D0 ~1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
) ^, l% j% _1 v' ^3 P1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
|9 J% Y9 E M( Z Q' V1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
( R$ G5 J" I" W3 c+ \2 v1236161 CONCEPT_HDL CORE Import Design shows the current project pages+ f/ s- z0 t* c( x/ n
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
! p( k2 D. r1 }( i6 Y- y0 c% [1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion$ `1 U% S( ~: d
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
1 ]- A" v% b$ F. N, h1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
4 f1 J! {+ Q2 N6 y0 ]* Z+ C/ f1 p1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
8 `& Z* v) y1 a$ c" ~1236781 F2B PACKAGERXL Export Physical produces empty files" N/ \) K( A( \' k0 L% m: J
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run# c" {. y( |9 g& D" `, n5 A ]
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
( O. t3 G+ ^- S$ f- _( N1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
- b, `3 e/ W, j6 _! n+ F1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.3 s! C0 D" W3 f! ^1 w& p/ p# ~
1238852 CAPTURE GENERAL signal list not updated for buses( N; x* E3 b8 G
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
) \' B4 n0 _# v, _" r+ X t1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
* Y5 N9 F4 w0 w6 A9 h% z. D x1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
5 V, M( V$ L0 a' x1239763 PSPICE PROBE Cannot modify text label if right y axis is active o5 S) `7 g/ e! ^6 n5 y C
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
% a- f3 i* E% F( g6 u- L1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
& v# l- X$ E0 L% _3 H1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
2 T8 R3 F- |# q1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file% E8 g7 S: y* a2 K; Z$ N: ]
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable' n- I: m5 x9 y. ~9 k5 k3 @
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy. T0 M8 s4 s. {3 |
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms, F. j2 e6 L: D
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working* X$ [ O: d( _5 y& W
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
4 j% J( \# Z( L2 ^1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
, g4 v; q( P+ X5 p. K" j1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning$ d- p$ k8 u3 M9 U: g; N
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
' _. U& q9 N4 z0 U, X; S1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
+ W3 x/ n+ @! ?" K2 `' G1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results, U" G! o' |3 P) p; ]) I
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
/ J" s4 a' U N+ s1 @1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
7 {" [/ O4 D; C+ L1 L; u1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
5 O9 n# T6 l D- ]( l) p2 D: p' c1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
# c7 @5 D! y6 {" E1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder2 S- @; A, z7 C6 D$ J* o
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
; p& _# T3 {) S5 T" r1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
' N# Y8 O B) z1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?- ^( E) S ^, Q5 ]0 o3 p* c
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character2 \5 d7 W1 x) s& ]9 g
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
) C- ?- I! |) {$ M1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown" a4 |2 z7 h. I
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
) }% [( {! Q! v+ _" _1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
+ q% |- {% ^9 i, S4 N$ v# E1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained7 d4 `3 p% e; i4 E2 N2 y6 x
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box9 Q+ y( N' e( a# p( Y4 }4 C
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
/ H# I; G: h* V! M/ Z' d1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
A2 ^; o# P) W" D- o) l2 R0 A1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts# E, L2 b0 a9 |9 Q" @
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.& m( o9 Z4 B" D5 [! Z' L1 T
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint: z: b3 Y2 v1 y' c4 r
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
6 j8 h0 V0 R6 N# t% D+ E- ]7 Z1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.& X9 V# p8 y1 c, t! ~" Y9 Z
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies# C/ `0 B' p2 |, v9 y H
1253424 SCM SCHGEN Export Schematics Crashes System Architect
: k( C# R3 d* N/ ?, U1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
- f! f0 ?# b6 R: s4 q7 [1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing/ m3 k' \2 u7 a9 z* L- W
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
; b+ w* U: k/ q1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error8 y1 G7 C( I1 ^! H1 D
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
3 [, S+ h2 Q: `4 u$ y4 D1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
, ?1 ^; Y0 _ Q% `! |1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects. V! b+ F* k2 }( Q. J1 |
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode; p7 E( r* T2 h0 U* V& C3 N
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
2 b: F# \/ w. W4 S6 a+ `1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE! o6 y- z% ]% V X4 H5 q0 Q/ F) z7 m
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool; R9 x$ P) s& |! A9 p; F+ ^1 h
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
) A* V8 g0 G6 O7 n1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library) n7 i; L( g7 Z: Y: w6 T" l4 @
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
5 f5 c u' O- e$ j. I; R1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash' T/ Z4 J k0 D
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
. @2 O+ I6 m$ ^/ n6 E2 N0 j% F1258029 APD WIREBOND The bondwire lost after import the wire information( M" k: k' `- u
1258979 APD NC NC Drill: There is difference of number of drills.( L: @7 F% S: p: V8 m8 F0 a
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
2 s# m( f% \3 d" ~% h1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
7 Z+ C( Q' t3 I. ]5 ]( m( Q [1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
$ P [9 L" u8 j1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
0 R+ c) g+ Q8 z# Y: U4 _! J1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void% p, h i6 e6 Y
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss, J' N$ Y$ K" q. V# D. _ g
, K7 U6 Q( \" h- b; x5 ]
|
|
電子產(chǎn)業(yè)一站式賦能平臺
窺視卡
置頂卡
變色卡
