SPB_16.6 27號(hào)補(bǔ)丁下載鏈接--Hotfix_SPB16.60.027_wint_1of1.exe

cesc

27號(hào)補(bǔ)丁修復(fù)的BUG較多！
百度網(wǎng)盤(pán)下載鏈接http://pan.baidu.com/s/1mgwSsPy

7 N  \3 M3 Z6 A  nDATE: 04-25-2014   HOTFIX VERSION: 027
- X3 k; N( k& [( P2 g( G% G===================================================================================================================================
7 P/ ?' D) [# ]9 g: S- PCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
, g5 |5 E, V7 ?===================================================================================================================================
2 Q, B4 _5 z; l5 ?308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
. `1 A' ~' H6 D# [% D" z481674  allegro_EDITOR pads_IN          No board file saved from pads_in
- d  |% N3 J5 C6 f( k1 R: T982929  allegro_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
4 D% ]1 H# }; U: U8 T2 q1012783 FSP            OTHER            Need Undo Command in FSP
1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
1072673 pcb_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
8 p  @' o, G' }) K, F1073231 CONCEPT_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
/ v3 u% p4 G5 o1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
$ s; C( t6 W- w. Z- U/ \* C5 m1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
3 o, J; Z- o% v' y" L) [7 z- ?1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
4 o9 d- j* N  b! c! h9 y1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.
) V# h1 _8 c% P1 ]8 m. B7 N1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings
1185575 SIP_layout     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
! F  g8 ~* \( _* \' R1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates
1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime
1208478 PSPICE         PROBE            Attached project gives overflow error with marching ON.
1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
3 e- ^) _) J& U1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?
2 S. W# j: |. E5 I1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.
1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values
, i- k, i; |' D1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging
3 k" n8 D8 X4 V' ?1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
3 [2 E. q" O6 S5 M, g$ Y" T1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes
1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux
& K  S) R  E* ?8 m0 {# W9 k; z1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
1221182 ADW            TDA              Team Design with SAMBA
1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair
1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened
$ U# f# k0 D% a5 C* f" R1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts
1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
9 V: y: T) S6 k4 S: I7 @4 \1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor
1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path
1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
' n) {+ `* ^5 \  G1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
3 r% H7 N' G9 Z  G1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property
1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet
1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal
1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
2 ^4 p" P9 k# M6 z: N9 o8 f( [1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration
- i1 W/ {9 r4 j" H; c1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case
4 r* {1 E8 _+ M% E( H, Y9 M1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
. \* `8 G1 `' J8 Q- H8 u" n) T1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
( x1 L; H" g# ?4 r! W1 @1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
) Y0 ^1 }# [$ ]: s- g1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
. T: w7 B& q  w5 p1230432 CONCEPT_HDL    CORE             No Description information in BOM
) B: i5 F) l0 ~1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes
1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files
- w% O8 U: R/ w- y% \: l' q1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets
1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
1232100 CONCEPT_HDL    SKILL            Unable to execute the SKILL commands in viewer mode
1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical
3 g1 m: ~/ S! @$ t% g1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
! v* S# S; \- P) d3 ?1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
; T2 D. P/ l: y% F* d1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved
6 a' y" n* d" \5 g+ ~) y1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect
0 f9 E/ A, D# E2 k% L1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set
4 ^1 H  `) a' }) D' L1 A( L1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
4 }6 x( _" P8 N: i, q; H9 }- w; s$ v1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages
, d* g* N- b  S3 f# H( ]$ V1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.
1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
/ P& [1 e/ [2 N( x! h6 H; P1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
4 v# W* {8 M. q8 L$ j1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
1236781 F2B            PACKAGERXL       Export Physical produces empty files
1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
8 Q& c7 x  u, A2 ~: x- K/ F7 f1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition
1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.
1238852 CAPTURE        GENERAL          signal list not updated for buses
1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes
5 @* p' r+ @8 l- a6 H9 L1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
* {1 g) x! e. O; U1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE
1 ]/ `2 ^) N7 D$ `  G) Z$ \" U1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
3 `5 @1 ?- e9 G3 [) s2 z1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable
1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
$ y4 |* r8 w! v" Z. @" H1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
; c% b: ]3 P+ a  Q. q- J' e1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working
1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.
1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side
1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
/ M" a  ?& j: i( R) H1 P2 M9 W1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
- F3 }0 g. F4 f! S# i& Z1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
# q8 ]. j  [9 ~! i6 x5 a2 @5 @1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring
1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder
1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
* }3 v* \  u" R. _2 `2 _1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design
1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
' F( K+ s; d, r0 u1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
, ~1 T" x2 ^$ [$ g; V1 L  Y1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
7 c9 R% g1 z/ b7 _$ ^! C+ M1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL
! G, |/ C( F9 x3 g2 X! V1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained
% M: X, H( ~/ @& ]$ P6 g1 d' N1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
, L" E- C2 r, V5 ~$ `4 d2 \/ ?1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
# X( S8 U! x( m6 X* C, Y6 I1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components
1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
! y: x2 K3 c; w& t1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
9 M- k) e" t4 d! W8 }# q1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
: l4 q. [6 N$ l9 _1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
& M7 V9 m: B4 y9 {1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router
1 f) W+ }! n$ L0 I/ [3 z' i4 [. J1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error
1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation
) z- \* ~3 R$ K4 U( n! m1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode
1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
  o9 R; E7 J! b8 ~1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
: G- E7 o# |" i3 U; Q* N7 O- I; |1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
) ?7 m1 Z# D+ D' y- f* U9 D- |1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash
  Y- G, [! u  l1 ?+ U( J1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time
1258029 APD            WIREBOND         The bondwire lost after import the wire information
/ g' u' b: P* j% Z  q' ]$ _1258979 APD            NC               NC Drill: There is difference of number of drills.
" |) M) s/ }& d1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
: n7 U& t/ J8 i  D3 d/ \2 B1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
" f$ G; B4 C5 U1 |8 ?4 l! D1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines
4 \' c3 D5 u2 t- a1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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