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分享:最新Hotfix_SPB17.20.022_wint_1of1補丁

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發(fā)表于 2017-6-30 08:36:09 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
Fixed CCRs: SPB 17.2 HF022
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========================================================================================================================================================( b  M% e, v1 U6 s7 {
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B1 }3 `% d& w2 F( m
========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s9 P: V" k3 `# A
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
9 f( h4 M4 `. e1 a+ I( e# {1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z
8 ^+ \5 S9 y$ \. ?2 @1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
. t; f# k+ I  F3 Y1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager% `: J0 [) a7 e2 J" U$ v
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications
0 a9 v, e9 @2 k/ u& d1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager+ {  Q. N8 c; Q: O( E# `. {
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X
, r) U6 T1 B# l, I) L1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B- u# a, u( q0 X" {1 q
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened
$ c5 Q8 T4 d+ w! C' X1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g
5 E# W; b9 g2 ]1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
5 i$ [3 t- O8 E! U/ b' u1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [! g) G7 R3 k& w' X
1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k
* N! C; R& `9 M: @8 |# {1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.
- ^: d' ^5 q6 ?% J+ R. B! L# g6 e1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
8 O0 u4 m& G: k  F) G7 Y1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
1 [8 Z, R3 o( l6 T  {) J" F# J1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @
2 U5 f, R9 f9 n; _# E1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool; ?( J/ g6 ]: ]( C- B2 l
1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s) ]* |  `" [7 f! R1 [" `# w
1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
9 J: }/ f$ a, h7 |( w% I% A8 a1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P$ G- r: O6 u8 _
1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-20162 N9 V, n) g) p+ u
1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
& e! y+ d* o" ^0 d2 E% D; y1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h  x9 E" j) W# W+ s
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
2 F# G4 i) u/ F! |  \9 A( }1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly9 L6 Q- a; Z: E6 J# l9 a; A3 {
1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H
  C9 o6 L& U: y; \1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B$ q0 m4 h+ y2 i# r8 E. O
1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
& j3 w/ _. \' F+ r/ _& e  `; B1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
/ Y3 U1 h6 ~& ^; E# S& F1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j
7 T' p; ], X" W9 S# V1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes/ \7 x7 j4 }9 \1 f) M# W6 S6 x2 ?8 w
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J
; ?) M; n! i$ F$ i1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]
( g2 {- I: h/ Y+ r8 d$ y1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \
6 Q! ?0 M: {0 q2 T; X1 Z( S/ p1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner, V6 ]! e; b6 X; L5 q
1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor3 ]; [) M& `5 @0 w
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
8 g  q# t" r1 O& S; c# b1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {! d0 T3 |  f# d6 N9 y
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O' H& w* {! F# X- x7 L
1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check. r, ]# r0 z3 I/ y2 `4 k( s
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鏈接:http://pan.baidu.com/s/1dFw4emH 密碼:smbg

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發(fā)表于 2022-5-10 09:14:55 | 只看該作者
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