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分享:最新Hotfix_SPB17.20.022_wint_1of1補(bǔ)丁

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發(fā)表于 2017-6-30 08:36:09 | 只看該作者 回帖獎(jiǎng)勵(lì) |倒序?yàn)g覽 |閱讀模式
Fixed CCRs: SPB 17.2 HF022
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========================================================================================================================================================
/ A- q, K1 D; j: ]: H$ w% rCCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B
' |) m( Q5 S5 w& L2 W========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s
8 U. c* g, q' X, @% q, o1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
( x7 z  d6 Y1 `) x+ c! l/ p1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z4 x) L7 F6 Q" w" C
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
. S" ~' j  A0 s; t7 c# m8 v1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager1 q* J9 n- M2 N0 C( B
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications
$ y7 O0 A+ [- Y6 R& |8 I& V1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager
2 s! x' E% t0 j4 O1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X
+ n4 @. l5 i, x; d5 B  j" a1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B; f8 _- f) i; Q* i+ R  b9 o
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened% R. Q. j7 Q% ?" V% \9 N2 b1 V
1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g
9 V/ [; v! y* v5 z1 u) a1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
3 w6 ]% m! v# x0 `1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [1 g* h* c9 M  j' A
1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k5 ~; \' E* s8 i
1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.
/ v; f7 Q! ?; q* t- O% i* o1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
/ E$ v4 }' W" F& o' p1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor, ~4 f8 X, Z$ C  o
1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @. N2 ~5 M4 \6 x
1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
* D5 R: v8 |2 o1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s
9 {/ v/ Z+ ^* E! i( E1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
& w5 A, M" M* z- m1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P2 F: ~: P  p9 R* w* u
1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016+ K: d6 W' L/ S( S5 ]
1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
1 I* P) Y9 J1 x5 V3 S5 `/ v1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h' \/ d' `$ A9 j% F  S
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
* n- o( H% Z, r* I7 J. k1 f1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly7 b% W# r/ e. r& l) C* l2 f9 a
1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H6 b4 {, E9 w% H" Q
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B1 `8 p1 ^+ n& ^$ F
1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
. E5 c( n0 r" f7 ]! j+ _( U1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic2 `1 P7 N7 x9 I6 Y3 N2 q; d2 A
1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j" h. [, j4 N9 @0 h) m
1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes5 l! a: ], V9 ]$ Q
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J
& E3 ~2 C% r+ ?1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]+ n2 m4 E) v* x( K& R
1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \( S/ S, f8 h  a/ W
1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
' ?, m1 m9 [" f" _) H: W1 k9 |4 z1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
5 H+ Y3 l- p9 @1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
+ Y; G+ o* e& Q1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {
6 y/ z& F' M) l* A1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O) s4 ]  M! r2 q& V) B! t( U% B" G& r
1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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- h% N  A5 a. _" {( H5 }4 R鏈接:http://pan.baidu.com/s/1dFw4emH 密碼:smbg

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發(fā)表于 2022-5-10 09:14:55 | 只看該作者
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