IP核的使用有什么要求嗎

張翔10 · 發(fā)表于 2022-11-3 13:51:18

剛接觸Verilog不久，需要做個FPGA解二階微分方程。
我用歐拉法解得，但調(diào)用IP核總是出毛病
比如
Error (10170): Verilog HDL syntax error at Eeler.v(22) near text "add_sub_inst";  expecting "<=", or "="
Error (10149): Verilog HDL Declaration error at Eeler.v(25): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(26): identifier "add_sub_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(27): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(28): identifier "add_sub_inst" is already declared in the present scope
Error (10170): Verilog HDL syntax error at Eeler.v(30) near text "$display";  expecting "endmodule"
Error (10759): Verilog HDL error at Eeler.v(30): object x declared in a list of port declarations cannot be redeclared within the module body
Error (10759): Verilog HDL error at Eeler.v(30): object y declared in a list of port declarations cannot be redeclared within the module body
Error (10759): Verilog HDL error at Eeler.v(30): object z declared in a list of port declarations cannot be redeclared within the module body
Error (10170): Verilog HDL syntax error at Eeler.v(30) near text ")";  expecting ";"
Error (10112): Ignored design unit "Eeler" at Eeler.v(1) due to previous errors
編的源程序這樣
module Euler
(
input wire          clk,
input wire [31:0] x,    //定義輸入量，單精度32位浮點(diǎn)數(shù)
input wire [31:0] y,
input wire [31:0] z,
input wire [31:0] h,
output wire n1
);

reg[31:0] z11;
reg[31:0] z1;
reg[31:0] y11;
reg[31:0] y12;
integer n;

initial
//開始迭代
for (n = 0; n < 10; n=n+1)
add_sub add_sub_inst( .clock ( clk),  .dataa ( x ),.datab ( h ),.result ( x ));
mult mult_inst( .clock ( clk ),  .dataa ( x),.datab ( z ),.result ( z11 ));
add_sub add_sub_inst( .clock ( clk),  .dataa ( z11 ),.datab ( y ),.result ( z1 ) );
mult mult_inst( .clock ( clk ),  .dataa ( h),.datab ( z),.result ( y11 ) );
add_sub add_sub_inst( .clock ( clk),  .dataa ( y ),.datab ( y11 ),.result ( y ) );
mult mult_inst( .clock ( clk ),  .dataa (h),.datab ( z1 ),.result ( z12 ));
add_sub add_sub_inst( .clock ( clk),  .dataa ( z ),.datab ( z12 ),.result ( z ) );

$display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
endmodule
想問一下，是IP調(diào)用有問題嗎？還是IP核不能在循環(huán)或函數(shù)里調(diào)用

xiaozhubanna · 發(fā)表于 2022-11-3 13:51:56

用另一種方式也有問題
module Euler
(
input wire          clk,
input wire [31:0] x,    //定義輸入量，單精度32位浮點(diǎn)數(shù)
input wire [31:0] y,
input wire [31:0] z,
input wire [31:0] h,
output wire n1
);

function [31:0] g;//加法器函數(shù)
  input reg [31:0] x;
  input reg [31:0] y;
      reg [31:0] z;
begin
add_sub add_sub_inst(
//調(diào)用浮點(diǎn)數(shù)加法IP
.clock ( clk),
.dataa ( x ),
.datab ( y ),
.result ( z )
);
g = z;
end
endfunction

function[31:0]f;    //乘法器函數(shù)
  input reg [31:0]x;
  input reg [31:0]y;
reg [31:0]z;
begin
mult mult_inst(
  //調(diào)用浮點(diǎn)數(shù)乘法IP
.clock ( clk ),
.dataa ( x),
.datab ( y ),
.result ( z )
);
  f = z;
end
endfunction

reg[31:0] z11;
reg[31:0] z1;
reg[31:0] y11;
reg[31:0] y12;
integer n;

initial
begin
                  //開始迭代
for (n = 0; n < 10; n=n+1)
   begin
      x = g(x,h);
      z11 = f(x,z);
      z1  = g(z11,y);
      y11 = f(h,z);
      y = g(y,y11);
      z12 = f(h,z1);
      z = g(z,z12);
   $display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
   end
end
endmodule
錯誤報告是
Error (10170): Verilog HDL syntax error at Eeler.v(16) near text "(";  expecting ";"
Error (10170): Verilog HDL syntax error at Eeler.v(33) near text "(";  expecting ";"
Error (10112): Ignored design unit "Euler" at Eeler.v(1) due to previous errors

IP核的使用有什么要求嗎

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