allegro Sigxplorer 差分信號仿真提示創(chuàng)建2-pin ESpice

焊武大帝

在Candence 16.6中Sigxplorer進行差分信號仿真提示：W- Automatically switching buffer delays from "on-the-fly" to "From Library" for diff
pair simulations. This is due to limitations of the Ibis standard for defining a
diff pair buffer delay test fixture. The suggested method for generating buffer
delays for a diff pair is to create a 2-pin ESpice device and use the assignment
mechanism in the "Differential Buffer Delays" form.
(Access in the IBIS Device Model Editor -> IBIS Device Pin Data -> Buffer Delays.)

該報錯會導(dǎo)致仿真參數(shù)直接將從"on-the-fly" 變成"From Library"
按照提示，我在對應(yīng)差分信號的模型中找到了對應(yīng)的ESPICE MODEl，那么這個2-pinESPICE MODEL如何創(chuàng)建，從哪里選擇？
差分信號的器件IBIS模型是從官網(wǎng)直接下載下來的