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Switch mode regulators5 g: l$ x, z* y* a, ^9 l
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
' o; K6 Y3 i1 x5 F f) C$ Yreceive power from VBAT or VCHG under application software control.
F( K9 D( z! M: P, u- OThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
- K5 m# \9 s2 d$ E! T1 n$ vVFBGA and the flash memory. The System SMPS can supply power to external components.
% m9 `( B: F. D( u6 u, ^3 M. KThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches- E, P) I k6 r: }, g, P
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.6 x2 \, q) V2 i+ M. N
The SMPS both have three operating modes:8 N% s9 H2 g0 G9 V
■ Normal (PWM)3 E2 c+ B. o9 E4 o$ k1 ]
■ Two low-power modes with reduced current capability:
& q ^; t2 V4 o2 j□ PFM
% ^' o( G3 R" y K□ ULP
, x+ m% ^5 ~ Y' Y' f2 [+ M xNormally the system auto switches, but this is optionally disabled.' l8 y t7 n$ z
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor., O: L( {# V$ g4 q8 {
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
) f- H( Z0 ^) [' pCH285-1).6 f1 G/ A7 X! d: ^4 B! e
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have6 _$ E. X$ X. t: `, d1 f" U6 L
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.& }6 w- v" }* I8 m
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
# o/ Q) E }* k% p1 o( ]5 ]( f5 j3 h2 h
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