|
|
Switch mode regulators
+ Z5 L. U, e# f2 r5 Q0 Q: KQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators: Q |* E. E! h- q
receive power from VBAT or VCHG under application software control.% ?4 g, S- \6 R( R9 h; F- O
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC30401 @( Y, F* }; D4 f' k6 x8 D5 t
VFBGA and the flash memory. The System SMPS can supply power to external components.0 P5 F, j0 V- E2 u3 v
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
8 g% C9 B: y' Y6 t/ D" Bbetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
/ }. T+ Z2 j- `: y; o& dThe SMPS both have three operating modes:
% v, s# l& U* f- N■ Normal (PWM)
2 B3 ~( Y" Q* a# _% h1 G: p2 I( v■ Two low-power modes with reduced current capability:
/ f4 ]' k/ n5 h# V+ z& y8 k: V□ PFM
2 ?- ]$ g: d: |" [/ x- ~, a7 u□ ULP
% M4 P8 W: H. M1 y% N) y# CNormally the system auto switches, but this is optionally disabled.: x2 @7 \( w7 ^$ U R
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.5 F1 P" K0 |& E6 r( L
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-/ K# G3 t2 _( ~; D, L
CH285-1).2 r8 Q s; B0 ?
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
7 R$ k; p2 _7 R8 B+ r& D9 X7 o4 ha 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point./ } w% w' G5 f4 V
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
) X6 P( \6 i1 ?6 u2 m0 f
1 L% q3 x# U% }/ a2 H7 z |
|
電子產(chǎn)業(yè)一站式賦能平臺
窺視卡
